1. Field of the Invention
The present invention relates to a receiver for an LCD source driver, and more particularly, to a receiver for an LCD source driver capable of reducing skew issue between different signals.
2. Description of the Prior Art
With rapid development of display technologies, traditional cathode ray tube (CRT) displays have been gradually replaced by flat panel displays (FPDs) that have been widely applied in various electronic products such as notebook computers, personal digital assistants (PDAs), flat panel televisions, or mobile phones. Common FPD devices include thin-film transistor liquid crystal display (TFT-LCD) devices, low temperature poly silicon liquid crystal display (LTPS-LCD) devices, and organic light emitting diode (OLED) display devices. The driving system of a display device includes a timing controller, a source driver, a gate driver and signal lines (such as clock lines, data lines and control lines) for transmitting various signals.
Reference is made to FIG. 1 and FIG. 2. FIG. 1 illustrates a prior art L-configuration LCD device 10, and FIG. 2 illustrates a prior art T-configuration LCD device 20. Each of the LCD devices 10 and 20 includes an LCD panel 12, a timing controller 14, a plurality of gate drivers 16, a plurality of source drivers CD1-CDn, and a plurality of signal lines. The timing controller 14 generates data signals DATA1-DATAm corresponding to images to be displayed by the LCD panel 12, setting signals for setting the pin voltage levels of the source drivers CD1-CDn, together with a clock signal CLK and control signals for driving the LCD panel 12. The setting signals shown in FIGS. 1 and 2 include DATAPOL signal, SHL/SHR signal for respectively setting the data-inversion pin, the shift-left/shift-right pin of the source drivers CD1-CDn. Another way to set the pin voltage levels of the source drivers CD1-CDn is to use pull-high or pull-low resistors on the driving system. The control signals shown in FIGS. 1 and 2 include latch control signal LD, polarity control signal POL, and start pulse signal SP. The start pulse signal SP is transmitted from the timing controller 14 to the source driver CD1 via a signal line of a transistor-transistor logic (TTL) interface, a complementary-metal-oxide-semiconductor (CMOS) interface or other compatible interfaces, and then from the source driver CD1 to subsequent source drivers sequentially. The clock signal CLK, the setting signals (DATAPOL, SHL/SHR), other control signals (LD and POL) and the data signals DATA1-DATAm are transmitted from the timing controller 14 to the source drivers CD1-CDn via corresponding signal lines of a reduced swing differential signaling (RSDS) interface. Among them, the setting signals (such as DATAPOL, SHL/SHR) can be also hard-wired set in the pins of the source drivers CD1-CDn. The control signals (such as LD and POL) can also be transmitted via a TTL interface, a CMOS interface or other compatible interfaces.
Reference is made to FIG. 3 for a functional diagram illustrating a source driver of the prior art LCD devices 10 and 20. The source driver of the prior art LCD devices 10 and 20 each includes a processing unit 32 and an RSDS receiver 34. The RSDS receiver 34 receives the data signals DATA1-DATAm and the clock signal CLK generated by the timing controller 14 and transmits the received signals to the processing unit 32. The processing unit 32, including an output buffer, a digital-to-analog converter (DAC) and a data latch, also receives control signals and setting signals generated by the timing controller 14, together with bias voltages for operating the output buffer, the DAC and the data latch. The control signals include polarity control signal POL, start pulse signal SP and latch control signals LD. The setting signals include DATAPOL, SHL, SHR, CSR, CS and LPC for respectively setting the data-inversion pin, the shift-left pin, the shift-right pin, the charge sharing/recycling enable pin, the channel select pin and the low power control pin of the source driver. The supply voltages include input voltages VCC, GND, VDDA, GNDA. The gamma reference voltages include VGMA.
In the prior art LCD devices 10 and 20, the data, clock, control and setting signals are transmitted via respective signals lines of an RSDS interface, a TTL interface or a CMOS interface. The RSDS/TTL/CMOS interface provides a bus type transmission that easily results in signal skewing, making it difficult to adjust timing parameters, such as the setup time or the hold time. Therefore, the data rate or the clock rate cannot be increased for high-speed operations in high-resolution display devices. Also, the clock and data signals are transmitted via different signal lines. With increasing demand for large-sized applications, the printed circuit board (PCB), on which the signal lines are disposed, also increases with panel size. Therefore, the trace delay from the timing controller to different source drivers also varies, thus making it even more difficult to adjust skew issue and the timing parameters. In the prior art LCD devices 10 and 20, various signals are transmitted via respective signals lines which occupy large circuit space on the PCB. The synchronization between the control signals and the clock signal in high-speed operations cannot be addressed by the prior art LCD devices 10 and 20. Also, setting signals are required for setting various pins of the source drivers (such as shift-right/shift-left pin, data-inversion pin, low-power-mode pin, and charge-sharing-mode pin) so that each source driver can function properly. Thus, the total number of input pins of the source drivers will be increased. Subsequently, the pin pitch of the source drivers has to be reduced and the yield of the bonding process will be lowered. The manufacturing costs of the display devices will be increased.